This invention relates to the field of integrated circuits. More particularly, this invention relates to the layout of power grid conductors within integrated circuits.
It is known to form integrated circuits with wires (conductors) formed to carry power and signals to be processed. Wire pitches (a pitch is the sum of the width and space of the wire) may no longer be single multiples of each other, e.g. half pitches may be used. SC (Standard Cell) placement and routing tools are predicated upon routing wires on predetermined pitches and at predetermined positions within critical layers. There are various industry placement and routing tools which follow these conventions. For example, the routing tool routes the wires based upon the M2 pitch and the standard cell is an integral (or on half integral) number of M2 pitches 6, 6.5, 7, 7.5, 9, 9.5, etc. The M1 wires are within the standard cell. M1 power wires may run parallel to the M2 power and signal routing wires, but other wires within the M1 layer may run both parallel to and perpendicular to the overlying M2 wires. Higher levels of wires (e.g. M3, M4, etc) may run in alternating perpendicular directions.
The M2 wires may placed on the pitch as illustrated by the solid wires indicated in FIGS. 4, 5 and 6 of the accompanying drawing. These pitches have usually been on simple multiples of each other, 1×, 1.5×, 2×, 3×, 4×. Typically the wires for the lower levels (M1, M2 etc) are both the thinnest (vertical thickness) and the smallest pitch (horizontal width and space). These wires connect to the transistor's gate, source, drain, and also connect to the thicker wires above. These thicker wires (vertical thickness) can carry more current, but are also a higher pitch (larger horizontal width and space).
Placement and routing tools seek to provide dense routing of power, ground, and signal wires through different layers of wires and the vias that connect the wires from different layers. They typically route wires on the M2 wiring track. When the wire pitches are no longer on simple multiples, then the least common multiples become quite large >5, 10, 40, 80. If one were to use the least common multiple between two wires, then the pitches can become so large that wiring density is sacrificed. In addition, it is not unusual for the wire that is closest to the transistors, typically called M1, to have a larger pitch than the M2 even though it is the same thickness. This is due to connectivity issues as it connects to the gate, source, and drain of transistors. In addition, the via placement also has become very problematic.
It is known to provide integrated circuits formed of a plurality of standard cells (SCs) connected to draw power from a plurality of standard-cell power conductors. These standard-cell power conductors are connected to power grid conductors in a different layer. The power grid conductors overlap (lie on top of) and have their longitudinal axis centered over the longitudinal axis of the standard-cell power conductors.
The conductor (track/wire) pitch within an integrated circuit is typically set to correspond to the sum of the minimum conductor width and the minimum conductor spacing of the manufacturing process such that substantially parallel conductors may be formed with closely packed positions. A problem with this approach is that when one of the powered grid conductors is made wider than normal, e.g. so as to reduce resistive losses within a power grid conductor, this wider conductor encroaches into the minimum conductor spacing such that an adjacent position for a track may not be used as otherwise that track would violate the minimum track spacing requirement.